The present application is based on Japanese priority application No. 2000-351444 filed on Nov. 17, 2000, the entire contents of which are hereby incorporated by reference.
This invention relates to semiconductor devices generally. Especially it is related to a non-volatile semiconductor memory and fabrication process thereof.
A flash memory is a non-volatile semiconductor memory that has a simple device structure suitable for high-density integration similar to DRAMs. Thus, it is used in the various information processing apparatuses including computers and cellular phones widely. Generally, a flash memory stores information in a floating gate electrode in the form of electric charges.
Recently, a non-volatile semiconductor memory having a MONOS (metal-oxide-nitride-oxide-semiconductor) structure or SONOS (semiconductor-oxide-nitride-oxide-semiconductor) structure has been proposed. These non-volatile semiconductor memory devices use an insulation film having an ONO structure for the gate insulation film of the MOS transistor and stores information in the ONO gate insulation film in the form of electric charges.
In the non-volatile semiconductor memory of such a MONOS structure or SONOS structure, injection of electric charges into gate insulation film is conducted from a drain side or a source side. As a result, storage of multivalent information becomes possible.
FIG. 1 is a diagram that shows the circuit construction of a NOR/AND type non-volatile semiconductor memory 10 that has a conventional SONOS structure.
FIG. 1 is referred to.
The non-volatile semiconductor memory 10 has a memory cell array M that includes plural memory cell transistors M11-Mmm, each having a gate insulation film of the ONO structure. In the memory cell array M, the memory cell transistors are arranged in a matrix formation. A group of memory cell transistors aligned in a row direction in the memory cell array M are connected commonly to any of the word lines WLn, WLn+1, WLn+2, WLn+3 . . . extending in a row direction at the respective gate electrodes. Furthermore, a group of memory cell transistors that are aligned in a column direction are connected in memory cell array M commonly to any of the data bit lines DBLh+1, DBLh+2, DBLh+3, DBLh+4 that extend in the column direction at the source diffusion region and the drain diffusion region.
Furthermore the non-volatile semiconductor memory 10 has select gate lines SG1,2,3,4, . . . The data bit lines DBLh and DBLh+2 are connected to the corresponding main bit lines MBLh by select transistors T1 and T2 connected to the select gate lines SG1 and SG2. Also, the data bit lines DBLh+1 and DBLh+3 are connected to the corresponding main bit line MBLh+l by select transistors T3 and T4 connected to select gate lines SG3 and SG4.
In, such a construction, information is written into the gate insulation film of the memory cell transistors M11, M12, . . . that has the ONO structure in the form of channel hot-electrons injected from the source region or drain region. The electric charges thus injected are held stably in the ONO film.
FIG. 2 shows the construction of a transistor 20 that constitutes the memory cell transistor M11, M12, . . . in the memory cell array M.
FIG. 2 is referred to.
The transistor 20 is formed of on a Si substrate 21. In the Si substrate 21, there are formed buried diffusion regions 21A and 21B respectively as the source region and drain region. Furthermore the surface of substrate 21 is covered with an ONO film 22 of the structure in which an oxide film 22a, a nitride film 22b and an oxide film 22c are stacked. Further, a polysilicon gate electrode 23 is formed on the ONO film 22.
FIGS. 3A and 3B are diagrams that show the writing operation and the erasing operation carried out in the memory cell transistor of FIG. 2, respectively.
FIG. 3A is referred to.
A source region 21A is grounded at the time of the writing of information and a large positive voltage +Vw is applied to the drain region 21B. Further, a large positive voltage +VG1 is applied to the gate electrode 23. As a result, hot-electrons are formed in the channel as a result of acceleration of electrons at the drain edge of the channel region. The hot-electrons thus formed are then injected into the ONO film 22. The hot electrons thus injected are held in the ONO film 22 in the vicinity of the drain edge. By exchanging the drive voltage that is applied to the drain region 21B and the source region 21A, it is also possible to carry out the injection of the hot electrons similarly in the vicinity of the source edge of the ONO film 22. As represented in FIG. 1, it becomes possible to write 2 bits of information for every one cell in the memory cell transistor 20 of FIG. 2.
When deleting information that is already written, a large positive voltage +Ve is applied to drain region 21B as represented in FIG. 3B. Furthermore a large negative voltage xe2x88x92VG2 is applied to the gate electrode 23. With this, holes are injected from drain region 21B into the ONO film 22. As a result, the electric charges that are accumulated in the vicinity of the drain edge in ONO film 22 are annihilated. In the case the electrons are accumulated in the vicinity of the source edge in ONO film 22, it is sufficient to carry out the hole-injection from source region 21A.
When reading out information written in the vicinity of the drain edge of the ONO film 22, a specified gate voltage Vg is applied to gate electrode 23 as represented in FIG. 4A. Further, the drain region 21B is grounded and the source region 21A is applied with a reading voltage Vr. As a result, it becomes possible for the careers to flow to the source region 21A from the drain region 21B through the channel formed in the Si substrate 21 right underneath the gate electrode 23, provided that electron are not accumulated in the vicinity of the drain edge of the ONO film 22. As a result, the memory cell transistor 20 conducts.
In the case the electrons are accumulated in the vicinity of the drain edge of ONO film 22 on the other hand, the channel right underneath the gate electrode 23 is blocked at the drain edge. Thus, the transistor 20 does not conduct. In the case of reading out the information written in the vicinity of the source edge of the ONO film 22, on the other hand, the source region 21A is grounded as represented in FIGS. 4A and 4B. Further, a read voltage Vr is applied to the drain region 21B.
FIGS. 5A-5D, FIGS. 6A-6C, FIGS. 7A-7D, FIGS. 8A-8C, FIGS. 9A-9D and FIGS. 10A-10C show the fabrication process of a non-volatile semiconductor memory 10 that uses the memory cell transistor 20.
FIGS. 5A-5D are referred to.
FIG. 5A is a plan view of the non-volatile semiconductor memory 10 while FIG. 5B shows the non-volatile semiconductor memory 10 in a cross-sectional view taken along a line X1-X1xe2x80x2 of FIG. 5A. FIG. 5C shows the non-volatile semiconductor memory 10 in a cross-sectional view taken along a line X2-X2xe2x80x2 of FIG. 5A. Further, FIG. 5D shows the non-volatile semiconductor memory 10 in a cross-sectional view of taken along a line X3-X3xe2x80x2 of FIG. 5A.
FIGS. 5A-5D are referred to.
An active region is defined on the Si substrate 21 by a field oxide film 21F having a thickness of 200-500 nm formed by a thermal oxidation processes at 900-1000xc2x0 C. Further, an ONO film 22 is formed on the active region. More specifically, the surface of the Si substrate 21 exposed at the active region is thermally oxidized at 800-1100xc2x0 C. As a result, an oxide film 22a is formed with a thickness of 5-10 nm. Furthermore, a CVD process is conducted at 600-800xc2x0 C. on the oxide film 22a. Thereby, a nitride film 22b is deposited with a thickness of 12-16 nm. Furthermore an oxide film 22c is formed on the nitride film 22b by a wet oxidation processes at 1000xcx9c1100xc2x0 C. with a thickness of 5-10 nm.
In the process of FIG. 5A, a resist pattern R1 is formed on the ONO film 22 thus formed such that the resist pattern R1 has an opening corresponding to each of data bit lines DBL to be formed, and As+ ions are introduced into the Si substrate 21 through the resist opening by an ion implantation process with a dose of 2xc3x971015xcx9c5xc3x971015 cmxe2x88x922 under an accelerating voltage of 50xcx9c90 keV. As a result, a number of n-type diffusion regions 21D corresponding to the data bit lines DBL are formed in the Si substrate 21 in parallel with each other. In the following, the n-type diffusion region 21D will be designated as bit-line diffusion region.
In the state of FIG. 5A-5D, the same cross-sectional structure appears in the cross-sectional view of FIGS. 5B-5D.
FIG. 6A shows the cross-sectional diagram taken along a line Y-Yxe2x80x2 of FIG. 5A, while FIG. 6B shows the cross-sectional diagram of the n-channel peripheral transistor used in the non-volatile semiconductor memory 10. Further, FIG. 6 C shows the cross-sectional diagram of the p-channel peripheral transistor that is used in the non-volatile semiconductor memory 10.
FIG. 6A is referred to.
It can be seen that the bit-line diffusion region 21D extends in the active region defined by the field oxide film 21F in the extending direction of the data bit line DBL continuously. As can be seen in FIGS. 6B and 6C, the p-channel peripheral transistor region and the n-channel peripheral transistor region are covered by a resist pattern R1 in the state of FIG. 5(A). Thus, no ion implantation is caused into the substrate in the state of FIG. 6A into the peripheral transistor region.
Next, the resist pattern R1 is removed in the step of FIGS. 7A-7D, and plural polysilicon gate electrode patterns 23 (referred to hereinafter as word line electrode) are formed on the Si substrate 21 in correspondence to the word line WL of FIG. 1, such that each polysilicon gate electrode patterns 23 extends in a direction generally perpendicular to the extending direction of the diffusion regions 21D.
Furthermore, a channel-stop diffusion region 21d is formed between the bit-line diffusion regions 21D by an ion implantation process of B that introduces B ions into the Si substrate 21. During the ion implantation process, the word line electrode 23 is used as a mask. The ion implantation process may be conducted with a dose of 3xc3x971012-1xc3x971013 cmxe2x88x922 under acceleration voltage of 50-80 eV as shown in FIG. 7B or FIG. 7D. It should be noted that FIG. 7A shows the non-volatile semiconductor memory 10 in a plan view.
Further, it should be noted that FIGS. 7B-7D show the cross-sectional views respectively taken along a line X1-X1xe2x80x2, a line X2-X2xe2x80x2 and a line X3-X3xe2x80x2 of FIG. 7A. As shown in FIG. 7C, the channel-stop diffusion region 21d is not formed right underneath the word line electrode 23. In FIGS. 7B and 7C, the channel-stop diffusion region 21d is formed also in the bit-line diffusion region 21D. In FIGS. 7(B) and 7C, the illustration of the channel-stop diffusion region 21d is omitted because very small impurity concentration level there in.
FIG. 8A shows the cross-sectional diagram of FIG. 7A taken along the line Y-Yxe2x80x2.
FIG. 8A is referred to.
It can be seen that plural word line electrodes 23 are formed repeatedly with a regular interval on the ONO film 22. Also, the channel-stop diffusion region 21d is formed at the edge part of diffusion region 21D as a result of the ion implantation of B.
The ONO film 22 is removed in the step of FIG. 7A by a mask process from the region of the peripheral transistor, after the step of removal of resist pattern R1 but before the step of formation of the word line electrode 23. Furthermore, thermal oxidation processes is conducted at 800-1100xc2x0 C. Thus, a thermal oxide film 22ox is formed typically with a thickness of 5-15 nm as shown in FIGS. 8B and 8C. As the ONO film 22 is already formed in the memory cell region M, formation of new oxide film does not occur even when such a thermal oxidation process is conducted. Furthermore, gate electrodes 23G1 and 23G2 are formed on the thermal oxide film 22ox thus formed simultaneously to the formation of the word line electrode 23, as shown in FIGS. 8B and 8C.
Because the data bit line DBL is provided by the diffusion region 21D in the non-volatile semiconductor memory 10, it is necessary and desirable to decrease the resistance of the bit line. Thus, as shown in FIGS. 9A-9D, an interconnection pattern 24M is provided on the diffusion region 21D in correspondence to the data bit line DBL such that the interconnection pattern 24M extends parallel with the diffusion region 21D. It should be noted that FIG. 9A shows the plan view of the non-volatile semiconductor memory 10. Also, FIGS. 9B-9D show the cross-sectional diagram of FIG. 9A taken along the lines X1-X1xe2x80x2, X2-X2xe2x80x2, and X3-X3xe2x80x2.
FIGS. 9B-9D are referred to.
An interlayer insulation film 25 is formed so as to cover the word line electrode 23 on the Si substrate 21. A contact hole 25A is formed in the interlayer insulation film 25 by a dry etching process so as to expose the diffusion region 21D. Thereby, the metal interconnection pattern on the interlayer insulation film 25 makes a contact with the diffusion region 21D at the contact hole 25A.
As shown in FIGS. 9A and 9C, a contact hole 25B is formed also on the interlayer insulation film 25 so as to expose the word-line electrode 23. Further, an interconnection pattern 24N is formed on the interlayer insulation film 25 in electric connection with the corresponding the word line electrode 23 at the contact hole 25B.
FIG. 10 shows the cross-sectional diagram of FIG. 9A taken along the line Y-Yxe2x80x2.
FIG. 10A is referred to.
Each of the word line electrodes 23 has a sidewall insulation film 23S thereon. The word line electrode 23 makes a contact with the diffusion region 21D through the contact hole 25A at plural locations in the extending direction thereof. When forming such a sidewall insulation film 23S, an insulation film is deposited on the Si substrate 23 so as to cover the word line electrode 23. Next, the insulation film is etched back by an anisotropic etching process that acts perpendicularly to the substrate principal surface. In the n-channel or p-channel peripheral transistor region, on the other hand, the structure of FIGS. 8B and 8C is covered, after formation thereof, by a resist film (not illustrated). Furthermore, a resist opening is formed in the resist film in the process of Figure lOB. By introducing an n-type dopant through such a resist opening by an ion implantation process, an nxe2x88x92-type LDD region 21 is formed in the Si substrate 2 at both lateral sides of the gate electrode 23G1.
Next, the resist film is removed. Furthermore, another resist film (not shown) is formed in the process of FIG. 10C and a p-type dopant is introduced through a resist opening therein by an ion implantation process. Thereby, a pxe2x88x92-type LDD region 21lp is formed at both lateral sides of the gate electrode 23G2.
Furthermore, a sidewall insulation film is formed to the sidewall of the gate electrodes 23G1 and 23G2 simultaneously to the sidewall insulation film 23S formed on the word line electrode 23 after removal of the resist film. Furthermore, a diffusion region 21n of n+-type is formed outside the sidewall insulation film provided on the gate electrode 23G1 in the n-channel peripheral transistor of FIG. 10B, by conducting an ion implantation process.
Further, a diffusion region 21p of p+-type is formed outside the sidewall insulation film of the gate electrode 23G2 in the p-channel peripheral transistor of FIG. 10C.
In the step of FIGS. 10(B) and 10(C), the contact holes 25C and 25D thus formed in the interlayer insulation film 25, which covers the gate electrode 23G1 and 23G2 on the Si substrate 21, expose the diffusion regions 21n and 21p. Thereby, the metal interconnection pattern 24W formed on the interlayer insulation film 25 makes a contact with the diffusion region 21n in such a contact hole. Further, the metal interconnection pattern 24V makes a contact with the diffusion region 21p. 
Meanwhile, there exists stringent demand of high speed operation similar to the one imposed to other high-speed semiconductor devices, also in the conventional non-volatile semiconductor memory 10. Because of this, there is a need of reducing the surface contact resistance as much as possible in the word line electrode 23, in the gate electrodes 23G1 and 23G2, and in the surface of the diffusion region 21D or the diffusion regions 21n and 21p. 
In the example of FIGS. 11A-11D, the silicide layer 26 is formed on the surface of the Si substrate 21 as shown in FIGS. 11A, 11B and 11D. The contact hole 25A of the interlayer insulation film 25 is formed such that the silicide layer 26 is exposed. Also, the silicide layer 26 is formed on the word line electrode 23. Furthermore, the silicide layer 26 is formed on the surface of substrate 21 along the bitline diffusion region 21D as shown in FIG. 12A, except for the part where the word line electrode 23 is formed. Furthermore, the silicide layer 26 is formed on the surface of the n+-type diffusion region 21n and on the surface of the p+-type diffusion region 21p, as can be seen in FIGS. 12B and 12C.
Such a silicide layer 26 can be formed by using the word line electrode 23 and also the gate electrodes 23G1 and 23G2 as a self-aligned mask in the process of FIGS. 7A-7D or in the process of FIGS. 8A-8C. After removing the ONO film 22 by a pyro-phosphoric acid treatment and a HF treatment, a refractory metal layer of W is deposited. The W layer thus deposited is caused to react with Si of the underlying layer. Especially, as shown in FIGS. 12B and 12C, the contact resistance of the semiconductor device, which is demanded to provide especially high-speed operation, is reduced, by forming the silicide layer 26 on the surface of the diffusion region 26 of the peripheral transistor. Thereby, the problem of signal delay that originates from the contact resistance is effectively reduced.
In the structure of FIGS. 11A-11D or FIGS. 12A-12C, it is very important that the silicide layer 26 is formed in correspondence to the contact hole 25A that is formed in the interlayer insulation film 25 as shown in FIG. 11B or in FIG. 12A. As explained before, the dry etching process that removes the oxide film is performed so as to reduce the contact resistance in the contact holes 25 C and 25D and in the contact hole 25A as represented in FIGS. 12B and 12C. Thus, the dry etching process has to be carried out such that the silicide layer 26 is not etched. In the event the silicide layer 26 is not formed in these regions, the dry etching would invade into the diffusion region 21D and reach the Si substrate 21. When this occurs, the desired device characteristic is no longer obtained.
However, the constitution of FIGS. 11A-11D has a fatal problem in that adjacent diffusion regions 21D easily cause short-circuit via the silicide layer 26 as represented in the cross-sectional diagram of FIG. 11B by *. In the cross-section of FIGS. 11B-11D, the conduction between the adjacent diffusion region 21D has to be caused as a result of the device operation. When this part causes short-circuit, the flash memory does not operate. On the other hand, the silicide layer 26 is indispensable at the contact hole 25A, as explained previously.
FIGS. 13A-13D and FIGS. 14A-14C show an example that is conceivable for overcoming the foregoing problem.
First FIG. 14A is referred to.
In the illustrated structure, the process of forming the sidewall insulation films 23W1 and 23W2 on the gate electrodes 23G1 and 23G2 in the peripheral transistor of FIGS. 14B and 14C is conducted by a deposition and etch back process of the insulation film 23W, wherein the deposition and etch back process is conducted while leaving the insulation film 23W deposited on word line electrode 23 selectively in the memory cell region M. For this purpose, a resist pattern is used.
Furthermore, an opening 23WA is formed in the insulation film 23W in correspondence to the contact hole 25A as represented in FIGS. 13B and 13C, and an opening 23WB is formed in correspondence to the contact hole 25B. Further, the silicide layer 26 is formed on bit-line diffusion region 21D in correspondence to such an opening 23A. Further, the silicide layer 26 is formed on the word line electrode 23 in correspondence to the opening 23B.
According to such constitution, the insulation film 23W exists between a pair of adjacent bit-line diffusion regions 24D. Therefore, no silicide layer 26 that may cause short-circuit is formed between the bit-line diffusion regions 24D.
However, there exists a limit in the patterning precision, and there inevitably appears a limit in the integration density when the non-volatile semiconductor device 10 is to be formed according to such a process in which the silicide layer 26 is formed in the memory cell array M selectively in the openings 23WA and 23WB of the insulation film 23. As explained before, the silicide layer 26 has to be formed positively right underneath the contact holes 25A and 25B in relation to the process of removing the native oxide film by the dry etching process.
Accordingly, it is a general object of the present invention to provide a novel and useful non-volatile semiconductor memory device and the fabrication process wherein the foregoing problems are eliminated.
Another and more specific object of the present invention is to provide a non-volatile semiconductor memory device of SONOS type or MONOS type having a self-aligned silicide layer on a contact region and is capable of eliminating short circuit between diffusion regions positively.
Another object of the present invention is to provide a non-volatile semiconductor device, comprising:
a semiconductor substrate carrying an active region defined by a device isolation structure thereon;
a plurality of diffusion regions formed in said active region with a separation from each other, each of said plurality of diffusion regions extending in a first direction;
a word line electrode extending over said active region in a second direction crossing said first direction; and
a charge storable insulation film formed on said active region in correspondence to said word line electrode between a surface of said active region and said word line electrode, said charge storable insulation film having a stacked structure in which a nitride film and an oxide film are stacked consecutively on an oxide film,
said device isolation structure having a plurality of openings each exposing said surface of said substrate in correspondence to an extension part of said plurality of diffusion regions,
each of said plurality of diffusion regions having said extension part extending into corresponding one of said plurality of openings;
each of said plurality of diffusion regions carrying a silicide film on a surface thereof.
Another object of the present invention is to provide a method of fabricating a non-volatile semiconductor memory device on a semiconductor substrate having a memory cell region and a peripheral circuit region, comprising the steps of:
defining an active region on said memory cell region of said semiconductor substrate by forming a device isolation film;
forming a charge storable insulating film on said active layer;
forming a plurality of bit-line diffusion regions in said active region such that each of said bit-line diffusion region extend parallel with each other in a first direction;
forming a word line electrode on said active region so as to extend in a second direction crossing said first direction and forming simultaneously a gate electrode on said peripheral circuit region of said semiconductor substrate;
forming a sidewall insulation film on both sidewall surfaces of said gate electrode in said peripheral circuit region;
forming first and second diffusion regions in said peripheral circuit region at both sides of said gate electrode while using said gate electrode and said sidewall insulation film as a mask; and
forming a silicide layer on a top surface of said gate electrode and a surface of said first and second diffusion regions,
said step of defining said active region comprising the step of forming a plurality of openings exposing a surface of said semiconductor substrate in said device isolation film along an edge part of said active region, such that said surface of said semiconductor substrate is exposed continuously from said active region to an outside of said active region,
said step of forming said plurality of bitline diffusion regions being conducted such that each of said plurality of bit-line diffusion regions extends continuously from said active region to a corresponding one of said plurality of openings,
said step of forming said sidewall insulation film on said gate electrode comprising the steps of covering said gate electrode and said word line electrode by a common insulation film, and forming said sidewall insulation film by applying an etch back process to said common insulation film selectively in said peripheral circuit region while leaving said common insulation film on said active region,
said method of fabricating said non-volatile semiconductor memory device further comprising the step of forming a silicide layer on a surface of said bit-line diffusion regions extending into respective, corresponding openings,
said step of forming said silicide layer on said bit-line diffusion region conducted simultaneously to said step of forming a silicide layer on a surface of said first and second diffusion regions.
Another object of the present invention is to provide a method of fabricating a non-volatile semiconductor memory device on a semiconductor substrate having a memory cell region and a peripheral circuit region, comprising the steps of:
defining an active region on said memory cell region of said semiconductor substrate by forming a device isolation structure;
forming a charge storable insulation film on said active region;
forming a plurality of bit line diffusion regions in said active region such that each bit line diffusion region extends in a first direction with a separation from each other;
forming a conductor layer on said active region such that said conductor layer covers said active region entirely and simultaneously forming a gate electrode in said peripheral circuit region of said semiconductor substrate;
forming first and second diffusion regions in said peripheral circuit region at both lateral sides of said gate electrode while using said gate electrode and said sidewall insulation film as a mask;
forming a silicide layer on a top surface of said conductor layer and on a top surface of said gate electrode and on a surface of said first and second diffusion regions in said active region and in said peripheral circuit region; and
patterning said conductor layer in said active region to form a word line electrode extending in a second direction crossing said first direction,
said step of defining said active region including the step of forming a plurality of openings in said device isolation structure along an edge of said active region so as to expose a surface of said semiconductor substrate respectively in correspondence to said plurality of bit-line diffusion regions, such that said surface of said semiconductor substrate is exposed continuously form said active region to an outside of said active region,
said step of forming said plurality of bit line diffusion regions comprising the step of forming said bit-line diffusion regions such that each of said bit-line diffusion regions extend continuously from said active region to a corresponding one of said plurality of openings,
said method further comprising the step of forming a silicide layer on a surface of said plurality of bit-line diffusion regions each extending into corresponding one of said openings while using said common insulation film left on said active region as a mask,
said step of forming said silicide layer on said surface of said bit-line diffusion region being simultaneously to said step of forming said silicide layer on said word line electrode and on said first and second diffusion regions.
According to this invention, following advantageous features are obtained when forming a low-resistance silicide layer on the gate electrode or on the surface of the source/drain diffusion regions of the MOS transistor constituting a peripheral circuit of a non-volatile semiconductor memory, in that a silicide layer is positively formed by a self-alignment process in the memory cell region in correspondence to the part extending out from a memory cell region defined by a device isolation structure to the outside of the memory cell transistor. The extending part may be the one used for interconnection with a bit-line electrode pattern provided on an interlayer insulation film via a contact hole. As a result of the present invention, the active region of the memory cell region is positively prevented from being etched even when a dry etching process is applied in the peripheral circuit region as a pre-processing process for removal of native oxide film prior to the step of providing an interconnection pattern to the MOS transistor. As the present invention provides interconnection to the bit-line electrode pattern at a contact hole formed in the interlayer insulation film in correspondence to a device isolation region, the problem of short-circuit does not occur between the silicide layers that are formed in correspondence to respective bit-line diffusion regions.
In the non-volatile semiconductor memory device of this invention, it is desirable to form a silicide film on the surface of the diffusion region and further on gate electrode constituting the peripheral circuit region. Further, it is desirable to form the charge-accumulating insulation film so as to cover the entire surface of the active region continuously. Furthermore, there may be an insulation film formed so as to cover the surface and the sidewall surface of the word line electrode and the exposed substrate surface continuously. In this case, it is preferable that the insulation film covers the word line electrode in conformity with a shape thereof with a uniform thickness. Further, the insulation film covers the entire surface of the active region continuously. It is desirable that the interlayer insulation film covers the insulation film. Also, it is desirable that a silicide film is formed in the extending part of the word line electrode that extends outside the active region. It is desirable to form, in the interlayer insulation film, another contact hole outside the active region so as to expose the outside part. The silicide film may be formed on the word line electrode over the entire length thereof. In doing so, it is possible to form a sidewall insulation film on the extending part of the word line electrode extending the to the outside of the active region so that the sidewall insulation film encloses the active region. Such a sidewall insulation film composes a part of the insulating wall that towers from the substrate in a direction generally perpendicular to the substrate principal surface. In this invention the word line electrode can be formed of a conductive semiconductor material.
According to this invention, it becomes possible to form a silicide layer in a Si surface by a self aligned process in any of a memory cell region and a peripheral circuit region of a non-volatile semiconductor device having a charge storable insulation film. Thus, the problem of etching or attacking of the Si surface does not occur even when removal of natural oxide film is conducted by a dry etching at the time of forming a contact is formed on the Si surface, and deterioration of the device performance is successfully avoided. As a result of formation of the silicide layer, the non-volatile semiconductor memory of this invention has a preferable feature of reduced contact resistance. Thus, the non-volatile semiconductor device operates at high speed.
Other objects and further features of the present invention will become apparent from the following detailed description when read in conjunction with the attached drawings.